UPSD3433EV-40T6 STMicroelectronics, UPSD3433EV-40T6 Datasheet - Page 203
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UPSD3433EV-40T6
Manufacturer Part Number
UPSD3433EV-40T6
Description
MCU 8BIT 8032 128KB FLASH 52TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433EV-40T6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-TQFP, 52-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4908
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433EV-40T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
- Current page: 203 of 300
- Download datasheet (3Mb)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.2.7
Note:
Note:
1
2
The VM register
One of the csiop registers (the VM register) controls whether or not the 8032 bus control
signals RD, WR, and PSEN are routed to the Main Flash memory, or the Secondary Flash
memory. Routing of these signals to these PSM Module memories determines if memories
reside in 8032 program address space, 8032 XDATA space, or both. The initial setting of the
VM register is determined by a choice in PSDsoft Express and programmed into the
UPSD34xx in a non-volatile fashion using JTAG. This initial setting is loaded into the VM
register upon power-up and also loaded upon any reset event. However, the 8032 may
override the initial VM register setting at run-time by writing to the VM register, which is
useful for IAP.
Table 160 on page 203
Bit 7, PIO_EN, is not related to the memory manipulation functions of Bits 1, 2, 3, and 4.
SRAM and csiop registers are always in XDATA space and cannot reside in program space.
Figure 69 on page 204
PSEN to the memories on the PSD module. As an example, if we apply the value 0Ch to the
VM register to implement the memory map example shown in
the routing of RD, WR, and PSEN would look like that shown in
In this example, the configuration is specified in PSDsoft Express and programmed into the
UPSD34xx using JTAG. Upon power-on or any reset condition, the non-volatile value 0Ch is
loaded into the VM register. At runtime, the value 0Ch in the VM register may be changed
(overridden) by the 8032 if desired to implement IAP or other functions.
Table 160. VM register (address = csiop + offset E2h)
Default value of Bits 1, 2, 3, and 4 is loaded from Non-Volatile setting as specified from
PSDsoft Express upon any reset or power-up condition. The default value of these bits can
be overridden by 8032 at run-time.
Default value of Bit 7 is zero upon any reset condition.
I/O Mode on
I/O Mode on
0 = disable
1 = enable
Peripheral
Peripheral
PIO_EN
Port A
Port A
Bit 7
Bit 6
used
used
not
not
illustrates how the VM register affects the routing of RD, WR, and
defines bit functions within the VM register.
Bit 5
used
used
not
not
Main Flash
WR cannot
Main Flash
Main Flash
0 = RD or
1 = RD or
WR can
XDATA
access
access
space
Bit 4
Secondary
WR cannot
Secondary
Secondary
0 = RD or
1 = RD or
WR can
XDATA
access
access
space
Flash
Flash
Flash
Bit 3
Main Flash
can access
Main Flash
Main Flash
0 = PSEN
1 = PSEN
program
access
cannot
space
Bit 2
Figure 63 on page
Figure 70 on page
Secondary
can access
Secondary
Secondary
0 = PSEN
1 = PSEN
program
cannot
access
space
Flash
Flash
Flash
Bit 1
PSD module
198, then
not used
not used
204.
Bit 0
203/300
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