MC9S08SH4MTG Freescale Semiconductor, MC9S08SH4MTG Datasheet - Page 166

• Manufacturer Part Number: MC9S08SH4MTG
• Description: IC MCU 8BIT 4K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH4MTG

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Processor Series: S08SH
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.1.4
Figure 11-2
11.2
This section describes each user-accessible pin signal.
11.2.1
The bidirectional SCL is the serial clock line of the IIC system.
11.2.2
The bidirectional SDA is the serial data line of the IIC system.
11.3
This section consists of the IIC register descriptions in address order.
166
External Signal Description
Register Definition
Block Diagram
SCL — Serial Clock Line
SDA — Serial Data Line
is a block diagram of the IIC.
CTRL_REG
ADDR_DECODE
Control
Address
Clock
Input
Sync
Figure 11-2. IIC Functional Block Diagram
MC9S08SH8 MCU Series Data Sheet, Rev. 3
FREQ_REG
SCL
Arbitration
ADDR_REG
Control
Start
Stop
SDA
STATUS_REG
Interrupt
Compare
Register
Address
In/Out
Data
Shift
DATA_MUX
DATA_REG
Data Bus
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