MC9S08SH4MTG Freescale Semiconductor, MC9S08SH4MTG Datasheet - Page 217
![IC MCU 8BIT 4K FLASH 16-TSSOP](/photos/12/25/122597/mc9s08sh4mtg_sml.jpg)
MC9S08SH4MTG
Manufacturer Part Number
MC9S08SH4MTG
Description
IC MCU 8BIT 4K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH4CTJ.pdf
(338 pages)
Specifications of MC9S08SH4MTG
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must first be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
14.3.2.1
The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1.
Normally, a program would wait for TDRE to become set to indicate the last character of a message has
moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break
character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into
the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving
device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data
bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal
idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
14.3.3
In this section, the receiver block diagram
functional description. Next, the data sampling technique used to reconstruct receiver data is described in
more detail. Finally, two variations of the receiver wakeup function are explained.
The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in
SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop
bit of logic 1. For information about 9-bit data mode, refer to
For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full,
the data character is transferred to the receive data register and the receive data register full (RDRF) status
Freescale Semiconductor
Receiver Functional Description
Send Break and Queued Idle
BRK13
0
0
1
1
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Table 14-8. Break Character Length
M
(Figure
0
1
0
1
14-3) is used as a guide for the overall receiver
Break Character Length
10 bit times
11 bit times
13 bit times
14 bit times
Section 14.3.5.1, “8- and 9-Bit Data
Chapter 14 Serial Communications Interface (S08SCIV4)
Modes.”
217
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