C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 173
![IC MCU 8BIT 8KB FLASH 24QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051F902-GM
Manufacturer Part Number
C8051F902-GM
Description
IC MCU 8BIT 8KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F902-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 15x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
768 B
Interface Type
UART
Maximum Clock Frequency
25 MHz
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F912DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Package
24QFN EP
Device Core
8051
Family Name
C8051F90x
Maximum Speed
25 MHz
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1848-5
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18.2. Power-Fail (VDD/DC+ Supply Monitor) Reset
C8051F91x-C8051F90x devices have a VDD/DC+ Supply Monitor that is enabled and selected as a reset
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transition or power irregularity that causes VDD/DC+ to drop below V
be driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD/DC+ returns to a
level above V
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD/DC+ supply
monitor is enabled and selected as a reset source. The enable state of the VDD/DC+ supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD/DC+ supply monitor is de-selected as a reset source and disabled by software, then a software reset
is performed, the VDD/DC+ supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep
Mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below V
above V
source select state of the VDD/DC+ supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD/DC+ supply falls below the V
interrupt. See Section “12. Interrupt Handler” on page 120 for more details.
Important Note: To protect the integrity of Flash contents, the VDD/DC+ supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD/DC+ supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
VBAT
POR
VDD
V
V
WARN
while the user is replacing the battery. Upon waking from Sleep mode, the enable and reset
POR
RST
RST
WARN
VDDOK
SLEEP
RST
, the CIP-51 will be released from the reset state.
Power-Fail Reset
Active Mode
Figure 18.3. Power-Fail Reset Timing Diagram
POR
WARN
. A large capacitor can be used to hold the power supply voltage
VDD/DC+
VBAT
threshold. The VDDOK bit can be configured to generate an
Rev. 1.0
RAM Retained - No Reset
C8051F91x-C8051F90x
Sleep Mode
RST
will cause the RST pin to
Note: Wakeup signal
required after new
battery insertion
t
173
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