C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 201
C8051F902-GM
Manufacturer Part Number
C8051F902-GM
Description
IC MCU 8BIT 8KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F902-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 15x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
768 B
Interface Type
UART
Maximum Clock Frequency
25 MHz
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F912DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Package
24QFN EP
Device Core
8051
Family Name
C8051F90x
Maximum Speed
25 MHz
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1848-5
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Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
SmaRTClock Address = 0x04
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Name
Reset
Type
Bit
7
6
5
4
3
2
1
0
Bit
RTC0AEN SmaRTClock Alarm Enable.
RTC0CAP SmaRTClock Timer Capture.
RTC0SET SmaRTClock Timer Set.
Management” on page 143 for information on how to capture a SmaRTClock Alarm event using a flag which
is not automatically cleared by hardware.
MCLKEN Missing SmaRTClock Detector Enable.
OSCFAIL SmaRTClock Oscillator Fail Event Flag.
RTC0EN SmaRTClock Enable.
RTC0TR SmaRTClock Timer Run Control.
ALRM
Name
RTC0EN
R/W
7
0
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock
oscillator is disabled.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
SmaRTClock Alarm Event
Flag and Auto Reset
Enable.
Reads return the state of the
alarm event flag.
Writes enable/disable the
Auto Reset function.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
MCLKEN
R/W
6
0
OSCFAIL
Varies
R/W
5
RTC0TR
R/W
Rev. 1.0
Read:
0: SmaRTClock alarm
event flag is de-asserted.
1: SmaRTClock alarm
event flag is asserted.
4
0
C8051F91x-C8051F90x
Function
RTC0AEN
R/W
3
0
ALRM
R/W
2
0
Write:
0: Disable Auto Reset.
1: Enable Auto Reset.
RTC0SET RTC0CAP
R/W
1
0
R/W
0
0
201
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