C8051F902-GM Silicon Laboratories Inc, C8051F902-GM Datasheet - Page 200
![IC MCU 8BIT 8KB FLASH 24QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051F902-GM
Manufacturer Part Number
C8051F902-GM
Description
IC MCU 8BIT 8KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F902-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 15x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
768 B
Interface Type
UART
Maximum Clock Frequency
25 MHz
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F912DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Package
24QFN EP
Device Core
8051
Family Name
C8051F90x
Maximum Speed
25 MHz
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1848-5
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C8051F91x-C8051F90x
20.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the
ALARMn registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers.
If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm
event.
The SmaRTClock alarm event can be configured to reset the MCU, wake it up from a low power mode, or
generate an interrupt. See Section “12. Interrupt Handler” on page 120, Section “14. Power Management”
on page 143, and Section “18. Reset Sources” on page 171 for more information.
The following steps can be used to set up a SmaRTClock Alarm:
Notes:
•
•
•
20.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTClock timer and alarm have two operating modes to suit varying applications. The two modes
are described below:
Mode 1:
The first mode uses the SmaRTClock timer as a perpetual timebase which is never reset to zero. Every 36
hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software
managed and is added to the ALRMn registers by software after each alarm. This allows the alarm match
value to always stay ahead of the timer by one software managed interval. If software uses 32-bit unsigned
addition to increment the alarm match value, then it does not need to handle overflows since both the timer
and the alarm match value will overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a
need for a perpetual timebase. An example of an application that needs a perpetual timebase is one
whose wake-up interval is constantly changing. For these applications, software can keep track of the
number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year)
perpetual timebase.
Mode 2:
The second mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero
by hardware after each alarm. The alarm interval is managed by hardware and stored in the ALRMn
registers. Software only needs to set the alarm interval once during device initialization. After each alarm,
software should keep a count of the number of alarms that have occurred in order to keep track of time.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm
interval. This mode is the most power efficient since it requires less CPU time per alarm.
200
The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling SmaRTClock Alarm
Events (RTC0AEN = 0).
If AutoReset is disabled, disabling (RTC0AEN = 0) then Re-enabling Alarm Events (RTC0AEN = 1) after a
SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next alarm after 2^32
SmaRTClock cycles (approximately 36 hours using a 32.768 kHz crystal).
The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle. See Section
“14. Power Management” on page 143 for information on how to capture a SmaRTClock Alarm event using a flag
which is not automatically cleared by hardware.
1. Disable SmaRTClock Alarm Events (RTC0AEN = 0).
2. Set the ALARMn registers to the desired value.
3. Enable SmaRTClock Alarm Events (RTC0AEN = 1).
Rev. 1.0
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