HD64F3672FXV Renesas Electronics America, HD64F3672FXV Datasheet - Page 182

• Manufacturer Part Number: HD64F3672FXV
• Description: IC H8/3672 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FXV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Instruction Descriptions
2.2.53 (3) SHAL (L)
SHAL (SHift Arithmetic Left)
Operation
ERd (left arithmetic shift)
Assembly-Language Format
SHAL.L ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the left. The
most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Rev. 3.00 Dec 13, 2004 page 166 of 258
REJ09B0213-0300
Register direct
Addressing
Mode
Mnemonic
SHAL.L
C
ERd
MSB
Operands
b
31
ERd
1st byte
. . . . . .
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 31.
2nd byte
B
cleared to 0.
cleared to 0.
cleared to 0.
Instruction Format
— —
I
0 erd
UI
— —
H
3rd byte
LSB
b
0
U
N
0
4th byte
Shift Arithmetic
Z
V
States
No. of
C
2