C8051F34B-GM Silicon Laboratories Inc, C8051F34B-GM Datasheet - Page 150
![IC 8051 MCU 32K FLASH MEM 32-QFN](/photos/12/27/122778/c8051f34b-gm_sml.jpg)
C8051F34B-GM
Manufacturer Part Number
C8051F34B-GM
Description
IC 8051 MCU 32K FLASH MEM 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheet
1.C8051F349-GQ.pdf
(276 pages)
Specifications of C8051F34B-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFN
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1351-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F34B-GM
Manufacturer:
Silicon Labs
Quantity:
135
- Current page: 150 of 276
- Download datasheet (2Mb)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
15.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that
are both byte addressable and bit addressable. Port 4 (48-pin packages only) uses an SFR which is
byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output
data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the
XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can
always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write
instructions. The read-modify-write instructions when operating on a Port SFR are the following: ANL,
ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit
in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written
back to the SFR.
150
Bits7–0: P0.[7:0]
Bits7–0: Analog Input Configuration Bits for P0.7–P0.0 (respectively).
P0.7
R/W
R/W
Bit7
Bit7
Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is not configured as an analog input.
P0.6
R/W
R/W
Bit6
Bit6
SFR Definition 15.5. P0MDIN: Port0 Input Mode
P0.5
R/W
R/W
Bit5
Bit5
SFR Definition 15.4. P0: Port0 Latch
P0.4
R/W
R/W
Bit4
Bit4
Rev. 1.3
P0.3
R/W
R/W
Bit3
Bit3
P0.2
R/W
R/W
Bit2
Bit2
P0.1
R/W
R/W
Bit1
Bit1
(bit addressable)
P0.0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
Reset Value
Reset Value
11111111
11111111
0xF1
0x80
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