M30622SPGP#U3C Renesas Electronics America, M30622SPGP#U3C Datasheet - Page 102
![IC M16C MCU ROMLESS 100LQFP](/photos/12/28/122814/m30622spgp_u3c_sml.jpg)
M30622SPGP#U3C
Manufacturer Part Number
M30622SPGP#U3C
Description
IC M16C MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30622SPGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 10.3
System Clock Control Register 1
b7 b6 b5 b4
NOTES :
1.
2.
3.
4.
5.
6.
7.
After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), w ait tsu (PLL) elapses before setting the CM11
bit to “1” (PLL clock).
When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if
w riting to the CM10, CM11 bits.
When the PM22 bit in the PM2 register is set to “1” (on-chip oscillator clock is selected as w atchdog timer count
source), this bit remains unchanged even if w riting to the CM10 bit.
This bit is valid w hen the CM07 bit is set to “0” and the CM21 bit is set to “0”.
Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
When entering stop mode from high-speed or middle-speed mode, or the CM05 bit is set to “1” (main clock stops) in
low speed mode, the CM15 bit is set to “1” (drive capacity high).
This bit is valid w hen the CM06 bit is set to “0” (CM16 and CM17 bits enabled).
If the CM10 bit is set to “1” (stop mode), XOUT is held “H” and the internal feedback resistor is disconnected. The
XCIN and XCOUT pins are in high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the
CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
Jan 10, 2006
0 0 0
b3 b2 b1 b0
CM1 Register
Bit Symbol
(b4-b2)
Symbol
CM10
CM11
CM15
CM16
CM17
CM1
Page 85 of 390
—
All Clock Stop Control Bit
System Clock Select Bit 1
Reserved Bit
XIN-XOUT Drive Capacity
Select Bit
Main Clock Division Select Bit 1
(1)
(2)
Address
Bit Name
0007h
(4, 6)
(6, 7)
(3)
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
0 : Clock on
1 : All clocks off (stop mode)
0 : Main clock
1 : PLL clock
Set to “0”
0 : LOW
1 : HIGH
(5)
After Reset
00100000b
Function
10. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
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