M30622SPGP#U3C Renesas Electronics America, M30622SPGP#U3C Datasheet - Page 400
![IC M16C MCU ROMLESS 100LQFP](/photos/12/28/122814/m30622spgp_u3c_sml.jpg)
M30622SPGP#U3C
Manufacturer Part Number
M30622SPGP#U3C
Description
IC M16C MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30622SPGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Part Number
Manufacturer
Quantity
Price
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
25. Differences Depending on Manufacturing Period
Table 25.1 and Table 25.2 list the precautions are applicable or not applicable every chip version of M16C/62P flash
and ROM external versions. Contact separately about the mask ROM version.
Table 25.1
√ : Applies
− : Dose not apply
Ensure that RESET must hold valid-low state during power-on.
When using a reset IC, use a CMOS type IC. When using an
open-drain type reset IC, insert a capacitor between the reset
input and VSS. Adjust the R-C time constant between the
capacitor and pull-up resistor at least 10 times longer than the
VCC rising time.
If UART0 or UART1 are used as a slave in the I
or P6_5 are placed in a high-impedance state. P6_1 or P6_5
cannot be used as an output port even if the PD6_1 or PD6_5 bits
in the PD6 register are set to “1” (output mode). Therefore, set
the PD6_1 or PD6_5 bits to “0” (Input mode).
Do not enter wait mode when the main clock or on-chip oscillator
clock is selected as the CPU clock of which division is set by the
CM06 bit in the CM0 register, and the CM16 and CM17 bits in the
CM1 register.
The CM05 bit in the CM0 register is set to “0” (main clock
oscillation) and the CM02 bit is set to “1” (peripheral function
clock stops in wait mode).
Do not generate an NMI interrupt after entering mode.
Do not generate a voltage detection interrupt after entering
mode.
I/O ports (P0 to P5) will be indeterminate until internal power
supply is stable, such as when the power is turned on, if “H” is
applied to the CNVSS pin and “L” to the RESET pin while internal
power supply is unstable.
I/O ports (P6 to P14) will be indeterminate until internal power
supply is stable, such as when the power is turned on, if “H” is
applied to the CNVSS pin and “L” to the RESET pin while internal
power supply is unstable.
When the RESET pin is “L” in boot mode (apply “H” to the
CNVSS pin and P5_0 (CE), and “L” to the P5_5 (EPM)), internal
pull-up is enabled for P10_0 to P10_3, P11_0 to P11_7, P12_5
to P12_7, P13_0 to P13_7, P14_0 and P14_1 and so become “H”
level.
P0_0 to P0_7 and P1_0 to P1_7 may become indeterminate
when P8_4 is “H” and the RESET pin is “L” in boot mode (apply
“H” to the CNVSS pin and P5_0 (CE), and “L” to P5_5 (EPM)).
P0_0 to P0_7 and P1_0 to P1_7 are in a high impedance state
when the RESET pin and P8_4 are “L”.
Jan 10, 2006
Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (1)
Page 383 of 390
Precaution
2
C mode, P6_1
25. Differences Depending on Manufacturing Period
Chip Version
A
√
√
√
√
√
√
√
√
√
√
B
−
−
−
−
−
−
√
−
−
√
C
−
−
−
−
−
−
√
−
−
√
TECHNICAL UPDATE
TN-M16C-100-0309
TN-M16C-108-0309
TN-M16C-108-0309
TN-M16C-108-0309
TN-M16C-108-0309
TN-M16C-114-0310
TN-M16C-114-0310
TN-M16C-114-0310
TN-M16C-114-0310
Precaution 1.1
Precaution 1.2
Precaution 1.3
Precaution 1.4
Precaution 1.1
Precaution 1.1
Precaution 1.2
Precaution 1.3
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