M30622F8PGP#U7C Renesas Electronics America, M30622F8PGP#U7C Datasheet - Page 218

• Manufacturer Part Number: M30622F8PGP#U7C
• Description: IC M16C MCU FLASH 64K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30622F8PGP#U7C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.20
Table 17.9
17.1.2.1
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)
Bit Rate
(bps)
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table
17.9 lists Example of Bit Rates and Settings.
UiBRG count
source
RE bit in UiC1
register
RXDi
Transfer clock
RI bit in UiC1
register
RTSi
IR bit in SiRIC
register
14400
19200
28800
31250
38400
51200
The above timing diagram applies to the case where the register bits are set as follows:
Jan 10, 2006
i = 0 to 2
1200
2400
4800
9600
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
Receive Operation
Bit Rate
Example of Bit Rates and Settings
Count Source
of UiBRG
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
“H”
“1”
“0”
“1”
“0”
“L”
“1”
“0”
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Reception triggered when transfer clock
is generated by falling edge of start bit
Peripheral Function Clock : 16MHz
Set Value of
UiBRG : n
Start bit
103 (67h)
103 (67h)
31 (1Fh)
51 (33h)
25 (19h)
68 (44h)
51 (33h)
34 (22h)
25 (19h)
19 (13h)
Sampled “L”
Set to “0” by an interrupt request acknowledgement or by program
Bit Rate (bps)
D0
Receive data taken in
14493
19231
28571
31250
38462
50000
1202
2404
4808
9615
Transferred from UARTi receive
register to UiRB register
D1
Peripheral Function Clock : 24MHz
Set value of
UiBRG : n
D7
155 (9Bh)
155 (9Bh)
103 (67h)
77 (4Dh)
77 (4Dh)
28 (1Ch)
47 (2Fh)
38 (26h)
51 (33h)
38 (26h)
Stop bit
17. Serial Interface
Bit Rate (bps)
14423
19231
28846
31250
38462
51724
1202
2404
4808
9615