MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 49

MPU MX35 ARM11 400-MAPBGA

MCIMX357CJQ5C

Manufacturer Part Number
MCIMX357CJQ5C
Description
MPU MX35 ARM11 400-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Datasheets

Specifications of MCIMX357CJQ5C

Core Processor
ARM11
Core Size
32-Bit
Speed
532MHz
Connectivity
1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
400-MAPBGA
Processor Series
i.MX357
Core
ARM1136JF-S
Data Bus Width
32 bit
Data Ram Size
128 KB
Interface Type
I2C, JTAG, UART
Maximum Clock Frequency
532 MHz
Number Of Timers
3
Operating Supply Voltage
1.33 V to 1.47 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX357CJQ5C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX357CJQ5CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1
Freescale Semiconductor
SD10 and SD11 are determined by SDRAM controller register settings.
SD10
SD11
SD7
ID
SDCLK
CAS
CKE
ADDR
RAS
WE
CS
Address hold time
Precharge cycle period
Auto precharge command period
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 35
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Don’t care
BA
Table 35. SDRAM Refresh Timing Parameters (continued)
indicates SDRAM requirements. All output signals are driven by
Figure 30. SDRAM Self-Refresh Cycle Timing Diagram
1
Parameter
SD16
1
NOTE
Symbol
tAH
tRP
tRC
SD16
Min.
1.8
1
2
Max.
20
4
clock
clock
Unit
ns
49

Related parts for MCIMX357CJQ5C