MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 72

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1
2
3
where CEIL(X) rounds the elements of X to the nearest integers toward infinity.
4.9.13.2
Figure 52
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
72
Tdicd
IP16 Display interface clock low time
IP17 Display interface clock high time
IP18 Data setup time
IP19 Data holdup time
IP20 Control signals setup time to
ID
Tdicu
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
Display interface clock down time
Display interface clock up time
display interface clock
=
=
1
-- - T HSP_CLK ceil
2
1
-- - T
2
depicts the Sharp HR-TFT panel interface timing, and
HSP_CLK
Interface to Sharp HR-TFT Panels
Parameter
Table 53. Synchronous Display Interface Timing Parameters—Access Level
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
⋅
⋅
ceil
2 DISP3_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
2 DISP3_IF_CLK_UP_WR
--------------------------------------------------------------------- -
⋅
⋅
HSP_CLK_PERIOD
HSP_CLK_PERIOD
Symbol
Tdsu
Tdhd
Tckh
Tcsu
Tckl
Tdicd – Tdicu – 1.5
Tdicp – Tdicd +
Tdicu – 1.5
Tdicd – 3.5
Tdicp – Tdicd – 3.5
Tdicd – 3.5
Min.
Tdicd
Tdicp – Tdicd +
Tdicu
Tdicu
Tdicp – Tdicu
Tdicu
Table 54
2
Typ.
– Tdicu
1
lists the timing parameters. The
3
Tdicd – Tdicu + 1.5
Tdicp – Tdicd +
Tdicu + 1.5
Freescale Semiconductor
Max.
—
—
—
Units
ns
ns
ns
ns
ns