MCIMX515DJM8C Freescale Semiconductor, MCIMX515DJM8C Datasheet - Page 49

• Manufacturer Part Number: MCIMX515DJM8C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 20 C
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• Supply Voltage Range: 0.8V To 1.15V
• Operating Temperature Range: -20°C To +85°C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20
pF (except for NF16 - 40 pF) and there is max drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider.
frequency settings.
Freescale Semiconductor
Rounded up to whole nanoseconds.
emi_slow_clk (MHz)
133 (max value)
133
133
A potential limitation for minimum clock frequency may exist for some
devices. When the clock frequency is too low the actual data bus capturing
might occur after the specified trhoh (RE_B high to output hold) period.
Setting the clock frequency above 25.6 MHz (T = 39 ns) guarantees proper
operation for devices having trhoh > 15 ns. It is also recommended to set the
NFC_FREQ_SEL Fuse accordingly to initiate the boot with 33.33 MHz
clock.
Lower frequency operation can be supported for most available devices in
the market, relying on data lines Bus-Keeper logic. This depends on device
behavior on the data bus in the time interval between data output valid to
data output high-Z state. In NAND device parameters this period is marked
between trhoh and trhz (RE_B high to output high-Z). In most devices, the
data transition from valid value to high-Z occurs without going through
other states. Setting the data bus pads to Bus-Keeper mode in the IOMUX
registers, keeps the data bus valid internally after the specified hold time,
allowing proper capturing with slower clock.
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
nfc_podf (Division Factor)
Table 49. NFC Clock Settings Examples
5 (reset value)
4
3
NOTE
Table 49
enfc_clk (MHz)
demonstrates few examples for clock
33.25
44.33
26.6
Electrical Characteristics
T—Clock Period (ns)
38
31
23
1
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