MCIMX515DJM8C Freescale Semiconductor, MCIMX515DJM8C Datasheet - Page 79

• Manufacturer Part Number: MCIMX515DJM8C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 20 C
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• Supply Voltage Range: 0.8V To 1.15V
• Operating Temperature Range: -20°C To +85°C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.7.5
The FPM is a DPLL that converts a signal operating in the kilohertz region into a clock signal operating
in the megahertz region. The output of the FPM provides the reference frequency for the on-chip DPLLs.
Parameters of the FPM are listed in
1
4.7.6
This section describes the timing parameters of the HS-I
following modes: Standard, Fast and High speed.
Freescale Semiconductor
Reference clock frequency range—CKIL
FPM output clock frequency range
FPM multiplication factor (test condition is changed by a factor of 2)
Lock-in time
Cycle-to-cycle frequency jitter (peak to peak)
plrf = 1 cycle assumed missed + x cycles for reset deassert + y cycles for calibration and lock x[ts] = {2,3,5,9};
y[ts] = {7,8,10,14}; where ts is the chosen time scale of the reference clock. In this case reference clock = 32 kHz which makes
ts = 0, therefore total time required for achieving lock is 10(1+2+7) cycles or 312.5
FEC_MDIO (output)
FEC_MDC (output)
FEC_MDIO (input)
1
Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)
High-Speed I
See the errata for the HS-I
two standard I
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Figure 45. MII Serial Management Channel Timing Diagram
2
2
C (HS-I
C modules that have no errata.
Parameter
Table
Table 74. FPM Specifications
2
2
C) Timing Parameters
M12
C module in the i.MX51 Chip Errata. There are
74.
M13
NOTE
M14
2
C module. This module can operate in the
M10
M11
µ
s.
M15
Min
128
32
—
—
8
32.768
Electrical Characteristics
Typ
—
—
—
8
312.5
1024
Max
256
33
20
MHz
Unit
kHz
—
ns
µ
s
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