HD64F7044F28V Renesas Electronics America, HD64F7044F28V Datasheet - Page 34
HD64F7044F28V
Manufacturer Part Number
HD64F7044F28V
Description
IC SUPERH MCU FLASH 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD64F7044F28V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 3 Data Formats
3.3
Byte immediate data is located in an instruction code. Immediate data accessed by the MOV,
ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword data.
Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and is
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code but rather is stored in a
memory table. The memory table is accessed by a immediate data transfer instruction (MOV)
using the PC relative addressing mode with displacement. Specific examples are given in section
7, CPU Core Instruction Features, instruction 8, and table 7.4.
3.4
The SH-DSP uses three different data formats for instructions: the fixed decimal point data format,
the integer data format, and the logical data format.
The DSP type of fixed decimal point data format places a binary decimal point between bits 31
and 30. This data format can have guard bits, no guard bits, or be multiplication input. The valid
bit lengths and values displayed vary for each.
DSP type integer data formats place a binary decimal point between bits 16 and 15. This data
format can have guard bits, no guard bits, or be a shift amount. The valid bit lengths and values
displayed vary for each.
The shift amount for arithmetic shift (PSHA) is a seven-bit area between –64 and +63, although
only values between –32 and +32 are valid. The shift amount for logical shifts is a six bit area,
although, in the same fashion, only values between –16 and +16 are valid.
Rev. 5.00 Jun 30, 2004 page 18 of 512
REJ09B0171-0500O
Immediate Data Format
DSP Type Data Formats
Figure 3.3 Data Format in Memory (Little Endian)
Address 2n
Address 4n
Address m + 3
31
Byte
Address m + 2
Word
23
Byte
Longword
Address m + 1
15
Byte
Word
Address m
7
Byte
0
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