HD64F7044F28V Renesas Electronics America, HD64F7044F28V Datasheet - Page 44

• Manufacturer Part Number: HD64F7044F28V
• Description: IC SUPERH MCU FLASH 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD64F7044F28V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
4.2
Addressing modes effective address calculation by the CPU core are described below.
Table 4.7
Addressing
Mode
Direct
register
addressing
Indirect
register
addressing
Post-
increment
indirect
register
addressing
Pre-
decrement
indirect
register
addressing
Rev. 5.00 Jun 30, 2004 page 28 of 512
REJ09B0171-0500O
Addressing Modes
Addressing Modes and Effective Addresses
Instruction
Format
Rn
@Rn
@Rn +
@–Rn
Effective Addresses Calculation
The effective address is the content of register Rn.
The effective address is register Rn. (The operand is
the contents of register Rn.)
The effective address is the content of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, or 4 for a longword
operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for a
byte operation, 2 for a word operation, or 4 for a
longword operation.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rn
Rn
Formula
—
Rn
Rn
(After the
instruction is
executed)
Byte: Rn + 1
Word: Rn + 2
Longword:
Rn + 4
Byte: Rn – 1
Word: Rn – 2
Longword:
Rn – 4
(Instruction
executed with
Rn after
calculation)
Rn
Rn
Rn
Rn
Rn
Rn