PIC16F526-E/SL Microchip Technology, PIC16F526-E/SL Datasheet - Page 4

IC PIC MCU FLASH 1KX12 14SOIC

PIC16F526-E/SL

Manufacturer Part Number
PIC16F526-E/SL
Description
IC PIC MCU FLASH 1KX12 14SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets

Specifications of PIC16F526-E/SL

Core Size
8-Bit
Program Memory Size
1.5KB (1K x 12)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Type
FLASH
Ram Size
67 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 3x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Controller Family/series
PIC16F
No. Of I/o's
12
Eeprom Memory Size
64Byte
Ram Memory Size
67Byte
Cpu Speed
20MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ICE2000 - EMULATOR MPLAB-ICE 2000 POD
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC16F526
3.1.2.1
After receiving this command, the device will clock in
14 bits as a “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
FIGURE 3-2:
3.1.2.2
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The RB0
pin will go into Output mode on the second rising clock
FIGURE 3-3:
DS41317B-page 4
RB0
(ICSPCLK)
(ICSPDAT)
RB1
RB0
(ICSPDAT)
(ICSPCLK)
RB1
Load Data
Read Data
1
1
LOAD DATA COMMAND (PROGRAM/VERIFY)
READ DATA FROM PROGRAM MEMORY COMMAND
0
0
1
T
SET
2
0
1
2
1
1
T
3
SET
T
0
3
HLD
Input
1
T
1
HLD
4
0
0
4
1
5
5
x
x
T
6
DLY
x
6
x
T
T
1
T
DLY
DLY
DLY
2
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-2.
2
edge and it will revert back to Input mode (high-imped-
ance) after the 16th rising edge. Because this is a 12-bit
core, the two MSbs will read as ‘1’. A timing diagram of
this command is shown in Figure 3-3.
1
1
strt_bit
1
strt_bit
2
2
LSb
LSb
T
3
T
SET
DLY
3
-+
T
1
3
HLD
4
1
4
Output
© 2007 Microchip Technology Inc.
5
5
15
MSb
15
16
MSb
stp_bit
16
stp_bit
Input

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