PIC12F615-I/MS Microchip Technology, PIC12F615-I/MS Datasheet - Page 11
![IC PIC MCU FLASH 1KX14 8MSOP](/photos/6/59/65932/mfg_150_c04-111_ms_8-msop_sml.jpg)
PIC12F615-I/MS
Manufacturer Part Number
PIC12F615-I/MS
Description
IC PIC MCU FLASH 1KX14 8MSOP
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(26 pages)
3.PIC12F609T-ISN.pdf
(8 pages)
4.PIC12F615-ESN.pdf
(168 pages)
Specifications of PIC12F615-I/MS
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Number Of I /o
5
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS-232, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164325 - MODULE SKT FOR 8MSOPXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F615-I/MS
Manufacturer:
RICHTEK
Quantity:
5 400
Part Number:
PIC12F615-I/MS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.0
2.1
The PIC12F609/615/12HV609/615 has a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. Only the first 1K x 14 (0000h-
03FFh) for the PIC12F609/615/12HV609/615 is physi-
cally implemented. Accessing a location above these
boundaries will cause a wraparound within the first 1K
x 14 space. The Reset vector is at 0000h and the inter-
rupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
© 2006 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
Wraps to 0000h-07FFh
On-chip Program
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
PC<12:0>
Memory
13
0000h
0004h
0005h
03FFh
0400h
1FFFh
PIC12F609/615/12HV609/615
Preliminary
2.2
The data memory (see Figure 2-2) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. Register locations F0h-FFh in Bank 1 point
to addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0’ when read. The RP0 bit
of the STATUS register is the bank select bit.
RP0
2.2.1
The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615.
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
0
1
Note:
Data Memory Organization
Bank 0 is selected
Bank 1 is selected
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
GENERAL PURPOSE REGISTER
FILE
SPECIAL FUNCTION REGISTERS
Each
DS41302A-page 9
register
is