PIC12F609-I/MF Microchip Technology, PIC12F609-I/MF Datasheet - Page 34
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PIC12F609-I/MF
Manufacturer Part Number
PIC12F609-I/MF
Description
IC PIC MCU FLASH 1KX14 8-DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F609T-ISN.pdf
(26 pages)
4.PIC12F609T-ISN.pdf
(8 pages)
5.PIC12F615-EMF.pdf
(196 pages)
Specifications of PIC12F609-I/MF
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
5
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F609T-ISN PDF datasheet #4
- PIC12F615-EMF PDF datasheet #5
- Current page: 34 of 196
- Download datasheet (3Mb)
PIC12F609/615/12HV609/615
4.2
Every GPIO pin on the PIC12F609/615/12HV609/615
has an interrupt-on-change option and a weak pull-up
option. The next three sections describe these
functions.
4.2.1
The ANSEL register is used to configure the Input
mode of an I/O pin to analog. Setting the appropriate
ANSEL bit high will cause all digital reads on the pin to
be read as ‘0’ and allow analog functions on the pin to
operate correctly.
The state of the ANSEL bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
4.2.2
Each of the GPIO pins, except GP3, has an individually
configurable internal weak pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 4-5.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit of the
OPTION register). A weak pull-up is automatically
enabled for GP3 when configured as MCLR and
disabled when GP3 is an I/O. There is no software
control of the MCLR pull-up.
4.2.3
Each GPIO pin is individually configurable as an inter-
rupt-on-change pin. Control bits IOCx enable or disable
the interrupt function for each pin. Refer to Register 4-6.
The interrupt-on-change is disabled on a Power-on
Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set the GPIO Change Interrupt Flag bit
(GPIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the inter-
rupt by:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
DS41302B-page 32
Any read of GPIO AND Clear flag bit GPIF. This
will end the mismatch condition;
OR
Any write of GPIO AND Clear flag bit GPIF will
end the mismatch condition;
Additional Pin Functions
ANSEL REGISTER
WEAK PULL-UPS
INTERRUPT-ON-CHANGE
last read value is not affected by a MCLR nor BOR
Reset. After these resets, the GPIF flag will continue to
be set if a mismatch is present.
Note:
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
© 2008 Microchip Technology Inc.
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