PIC12F609-I/MF Microchip Technology, PIC12F609-I/MF Datasheet - Page 72
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PIC12F609-I/MF
Manufacturer Part Number
PIC12F609-I/MF
Description
IC PIC MCU FLASH 1KX14 8-DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F609T-ISN.pdf
(26 pages)
4.PIC12F609T-ISN.pdf
(8 pages)
5.PIC12F615-EMF.pdf
(196 pages)
Specifications of PIC12F609-I/MF
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
5
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F609T-ISN PDF datasheet #4
- PIC12F615-EMF PDF datasheet #5
- Current page: 72 of 196
- Download datasheet (3Mb)
PIC12F609/615/12HV609/615
9.1.6
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 9-4 shows the two output formats.
FIGURE 9-3:
9.2
9.2.1
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
9.2.2
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new
9.2.3
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion. Addi-
tionally, a 2 T
sition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
DS41302B-page 70
Note:
conversion result
Note:
(ADFM = 0)
(ADFM = 1)
ADC Operation
RESULT FORMATTING
STARTING A CONVERSION
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 9.2.6 “A/D Conversion
Procedure”.
COMPLETION OF A CONVERSION
TERMINATING A CONVERSION
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
AD
delay is required before another acqui-
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
Unimplemented: Read as ‘0’
ADRESH
10-bit A/D Result
MSB
bit 0
bit 0
9.2.4
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the F
option. When the F
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
F
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
9.2.5
The ECCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 counter resets to zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
See Section 10.0 “Enhanced Capture/Compare/
PWM (With Auto-Shutdown and Dead Band) Mod-
ule (PIC12F615/HV615 only)” for more information.
RC
, a SLEEP instruction causes the present conver-
bit 7
bit 7
ADC OPERATION DURING SLEEP
SPECIAL EVENT TRIGGER
10-bit A/D Result
LSB
RC
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
clock source is selected, the
ADRESL
bit 0
LSB
bit 0
RC
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