ATTINY20-CCUR Atmel, ATTINY20-CCUR Datasheet - Page 149

• Manufacturer Part Number: ATTINY20-CCUR
• Description: MCU AVR 2KB FLASH 12MHZ 15UFBGA
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-CCUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ATtiny20
If TWASIE in TWSCRA is set, a STOP condition on the bus will also set TWASIF. STOP condi-
tion will set the flag only if system clock is faster than the minimum bus free time between STOP
and START.
Writing a one to this bit will clear the flag. This flag is also automatically cleared when writing a
valid command to the TWCMDn bits in TWSCRB.
• Bit 5 – TWCH: TWI Clock Hold
This bit is set when the slave is holding the SCL line low.
This bit is read-only, and set when TWDIF or TWASIF is set. The bit can be cleared indirectly by
clearing the interrupt flags and releasing the SCL line.
• Bit 4 – TWRA: TWI Receive Acknowledge
This bit contains the most recently received acknowledge bit from the master.
This bit is read-only. When zero, the most recent acknowledge bit from the maser was ACK and,
when one, the most recent acknowledge bit was NACK.
• Bit 3 – TWC: TWI Collision
This bit is set when the slave was not able to transfer a high data bit or a NACK bit. When a col-
lision is detected, the slave will commence its normal operation, and disable data and
acknowledge output. No low values are shifted out onto the SDA line.
This bit is cleared by writing a one to it. The bit is also cleared automatically when a START or
Repeated START condition is detected.
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