ATTINY20-CCUR Atmel, ATTINY20-CCUR Datasheet - Page 78

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ATTINY20-CCUR

Manufacturer Part Number
ATTINY20-CCUR
Description
MCU AVR 2KB FLASH 12MHZ 15UFBGA
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY20-CCUR

Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-CCUR
Manufacturer:
Atmel
Quantity:
10 000
12. 16-bit Timer/Counter1
12.1
12.2
78
Features
Overview
ATtiny20
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement.
A simplified block diagram of the 16-bit Timer/Counter is shown in
actual placement of I/O pins, refer to
ters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in section
Figure 12-1. 16-bit Timer/Counter Block Diagram
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Timer/Counter
TCCRnA
OCRnB
OCRnA
TCNTn
ICRn
=
=
“Register Description” on page
Direction
Count
Clear
“Pinout of ATtiny20” on page
Control Logic
TOP
TCCRnB
Values
=
Fixed
TOP
ICFn (Int.Req.)
BOTTOM
Detector
Edge
clk
=
Tn
0
99.
OCnA
(Int.Req.)
OCnB
(Int.Req.)
Generation
Generation
Waveform
Waveform
Canceler
Noise
Clock Select
( From Prescaler )
Detector
2. CPU accessible I/O Regis-
Edge
Figure 12-1 on page
Comparator Ouput )
( From Analog
OCnA
OCnB
TOVn
(Int.Req.)
ICPn
Tn
8235B–AVR–04/11
78. For

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