ATTINY20-CCUR Atmel, ATTINY20-CCUR Datasheet - Page 28

• Manufacturer Part Number: ATTINY20-CCUR
• Description: MCU AVR 2KB FLASH 12MHZ 15UFBGA
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-CCUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.5
7.5
7.5.1
28
Register Description
ATtiny20
Port Pins
MCUCR – MCU Control Register
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
the I/O clock (clk
no power is consumed by the input logic when not needed. In some cases, the input logic is
needed for detecting wake-up conditions, and it will then be enabled. Refer to the section
Input Enable and Sleep Modes” on page 48
buffer is enabled and the input signal is left floating or has an analog signal level close to V
the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to
“DIDR0 – Digital Input Disable Register 0” on page 111
The MCU Control Register contains bits for controlling external interrupt sensing and power
management.
• Bit 5 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 4 – BODS: BOD Sleep
In order to disable BOD during sleep (see
logic one. This is controlled by a protected change sequence, as follows:
A sleep instruction must be executed while BODS is active in order to turn off the BOD for the
actual sleep mode.
The BODS bit is automatically cleared when the device wakes up. Alternatively the BODS bit
can be cleared by writing logic zero to it. This does not require protected sequence.
• Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2 - 0
These bits select between available sleep modes, as shown in
Table 7-2.
Bit
0x3A
Read/Write
Initial Value
1. Write the signature for change enable of protected I/O registers to register CCP.
2. Within four instruction cycles write the BODS bit.
SM2
0
0
0
ISC01
Sleep Mode Select
R/W
CC
7
0
I/O
/2 on an input pin can cause significant current even in active mode. Digital
) is stopped, the input buffers of the device will be disabled. This ensures that
SM1
ISC00
0
0
1
R/W
6
0
R
5
–
0
SM0
0
1
0
BODS
R/W
4
0
Table 7-1 on page
for details on which pins are enabled. If the input
SM2
R/W
Sleep Mode
Idle
ADC noise reduction
Power-down
3
0
for details.
SM1
R/W
2
0
25) the BODS bit must be written to
Table
SM0
R/W
1
0
7-2.
R/W
SE
0
0
MCUCR
8235B–AVR–04/11
“Digital
CC
/2,