ATTINY2313A-MUR Atmel, ATTINY2313A-MUR Datasheet - Page 10
ATTINY2313A-MUR
Manufacturer Part Number
ATTINY2313A-MUR
Description
MCU AVR 2K FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY2313A-MU.pdf
(270 pages)
Specifications of ATTINY2313A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
4 439
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4.4.1
10
ATtiny2313A/4313
The X-register, Y-register, and Z-register
Figure 4-2
Figure 4-2.
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in
Figure 4-3.
X-register
Y-register
Z-register
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Registers
Purpose
Working
General
shows the structure of the 32 general purpose working registers in the CPU.
Figure
AVR CPU General Purpose Working Registers
The X-, Y-, and Z-registers
4-2, each register is also assigned a data memory address, mapping them
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
7
XH
YH
ZH
0
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
…
…
0
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
Addr.
0x0D
0x0E
0x0F
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x00
0x01
0x02
0x10
0x11
Figure
4-3.
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte
XL
YL
ZL
0
8246A–AVR–11/09
0
0
0
0
0
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