ATTINY2313A-MUR Atmel, ATTINY2313A-MUR Datasheet - Page 139
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ATTINY2313A-MUR
Manufacturer Part Number
ATTINY2313A-MUR
Description
MCU AVR 2K FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY2313A-MU.pdf
(270 pages)
Specifications of ATTINY2313A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY2313A-MUR
Manufacturer:
LT
Quantity:
4 439
- Current page: 139 of 270
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14.10.4
8246A–AVR–11/09
UCSRC – USART Control and Status Register C
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char-
acter SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDR.
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
• Bits 7:6 – UMSEL1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in
Table 14-4.
Note:
• Bits 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the UPE Flag in UCSRA will be set.
Table 14-5.
Bit
0x03 (0x23)
Read/Write
Initial Value
UMSEL1
UPM1
1. For full description of the Master SPI Mode (MSPIM) Operation,
0
0
1
1
0
0
1
1
on page 145.
UMSEL1
UMSEL Bit Settings
UPM Bits Settings
R
7
0
UMSEL0
R/W
6
0
UMSEL0
UPM0
0
1
0
1
0
1
0
1
UPM1
R/W
5
0
UPM0
Mode
Asynchronous USART
Synchronous USART
Reserved
Master SPI (MSPIM)
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
R/W
4
0
USBS
R/W
3
0
UCSZ1
R/W
2
1
(1)
UCSZ0
R/W
1
1
Table
see “USART in SPI Mode”
UCPOL
14-4.
R/W
0
0
UCSRC
139
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