ATTINY44A-MMHR Atmel, ATTINY44A-MMHR Datasheet - Page 114
ATTINY44A-MMHR
Manufacturer Part Number
ATTINY44A-MMHR
Description
MCU AVR 4KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44A-MMHR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.3
13.3.1
114
Register Description
ATtiny24A/44A/84A
GTCCR – General Timer/Counter Control Register
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 13-2.
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
PSR10
clk
Bit
0x23 (0x43)
Read/Write
Initial Value
T0
I/O
1. The synchronization logic on the input pins (
Synchronization
TSM
R/W
Prescaler for Timer/Counter0
7
0
ExtClk
R
6
–
0
< f
Clear
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
R
4
–
0
T0)
is shown in
R
3
–
0
R
2
–
0
Figure 13-1 on page
clk
T0
R
1
–
0
PSR10
clk_I/O
R/W
0
0
8183C–AVR–03/11
113.
/2.5.
GTCCR
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