ATTINY44A-MMHR Atmel, ATTINY44A-MMHR Datasheet - Page 72
ATTINY44A-MMHR
Manufacturer Part Number
ATTINY44A-MMHR
Description
MCU AVR 4KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44A-MMHR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.6
72
Compare Match Output Unit
ATtiny24A/44A/84A
The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-
pare (0x) strobe bits in Normal mode. The OC0x Registers keep their values even when
changing between Waveform Generation modes.
Be aware that the COM0x[1:0] bits are not double buffered together with the compare value.
Changing the COM0x[1:0] bits will take effect immediately.
The Compare Output mode (COM0x[1:0]) bits have two functions. The Waveform Generator
uses the COM0x[1:0] bits for defining the Output Compare (OC0x) state at the next Compare
Match. Also, the COM0x[1:0] bits control the OC0x pin output source.
shows a simplified schematic of the logic affected by the COM0x[1:0] bit setting. The I/O Regis-
ters, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port
Control Registers (DDR and PORT) that are affected by the COM0x[1:0] bits are shown. When
referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If
a system reset occur, the OC0x Register is reset to “0”.
Figure 11-4.
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the out-
put is enabled. Note that some COM0x[1:0] bit settings are reserved for certain modes of
operation, see
COMnx1
COMnx0
FOCn
clk
I/O
“Register Description” on page 79
Compare Match Output Unit, Schematic
Waveform
Generator
D
D
D
PORT
OCnx
DDR
Q
Q
Q
1
0
Figure 11-4 on page 72
8183C–AVR–03/11
OCn
Pin
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