AT89LP216-20PU Atmel, AT89LP216-20PU Datasheet - Page 17

• Manufacturer Part Number: AT89LP216-20PU
• Description: MCU 8051 2K FLASH 20MHZ 16-PDIP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP216-20PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.2.2
3621E–MICRO–11/10
Reset Recovery from Power-down
Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0)
When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in
11-2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Figure 11-2. Interrupt Recovery from Power-down (PWDEX = 1)
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the falling edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in
to propagate to the CPU until after the timer has timed out. The time-out period is controlled by
the Start-up Timer Fuses. (See
a two clock cycle internal reset is generated when the internal clock restarts. Otherwise the
device will remain in reset until RST is brought high.
Figure 11-3. Reset Recovery from Power-down.
Internal
Internal
Internal
Internal
XTAL1
XTAL1
XTAL1
Clock
Clock
Reset
Clock
PWD
PWD
PWD
INT1
INT1
RST
Table 10-1 on page
Figure
t SUT
t SUT
15). If RST returns high before the time-out,
11-3. The internal clock will not be allowed
AT89LP216
Figure
17