ATTINY43U-SUR Atmel, ATTINY43U-SUR Datasheet - Page 51
ATTINY43U-SUR
Manufacturer Part Number
ATTINY43U-SUR
Description
MCU AVR 4KB FLASH 8MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY43U-SU.pdf
(182 pages)
Specifications of ATTINY43U-SUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.6
9.7
9.7.1
9.8
8048B–AVR–03/09
Watchdog Reset
Internal Voltage Reference
Watchdog Timer
Voltage Reference Enable Signals and Start-up Time
It is recommended to disable the BOD when using the integrated boost converter. See
Supply and On-Chip Boost Converter” on page 36
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
“Watchdog Timer” on page 51
Figure 9-6.
ATtiny43U features an internal bandgap reference. This reference is used for Brown-out Detec-
tion, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
turned on. The reference is on during the following situations:
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
9-3 on page
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
ACBG bit in ACSR).
CC
56. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Reset During Operation
Table 20-4 on page
for details on operation of the Watchdog Timer.
CK
158. To save power, the reference is not always
TOUT
“Power
Table
. See
51
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