ATTINY43U-MUR Atmel, ATTINY43U-MUR Datasheet - Page 107

• Manufacturer Part Number: ATTINY43U-MUR
• Description: MCU AVR 4KB FLASH 8MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.5
14.5.1
8048B–AVR–03/09
Alternative USI Usage
Register Descriptions
Half-Duplex Asynchronous Data Transfer
4-Bit Counter
12-Bit Timer/Counter
Edge Triggered External Interrupt
Software Interrupt
USICR – USI Control Register
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
Using the USI Data Register in three-wire mode it is possible to implement a more compact and
higher performance UART than by software, only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will increment the counter value.
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-
rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be
executed. See the USISIF bit description in
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when
the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.
See the USIOIF bit description in
• Bit 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected and will
always have the same function. The counter and Shift Register can therefore be clocked exter-
Bit
0x0D (0x2D)
Read/Write
Initial Value
USISIE
R/W
7
0
USIOIE
R/W
6
0
USIWM1
“Analog Comparator” on page 112
R/W
5
0
USIWM0
“Analog Comparator” on page 112
R/W
4
0
USICS1
R/W
3
0
USICS0
R/W
2
0
for further details.
USICLK
W
1
0
for further details.
USITC
W
0
0
USICR
107