AT90PWM1-16SU Atmel, AT90PWM1-16SU Datasheet - Page 198

• Manufacturer Part Number: AT90PWM1-16SU
• Description: MCU AVR 8K FLASH 16MHZ 24-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM1-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 24-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.8.4
19.8.4.1
198
AT90PWM1
ADC Result Data Registers – ADCH and ADCL
ADLAR = 0
Table 19-2.
1.
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the
ADCH register has also been read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the
result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read
ADCH to have the conversion result.
Bit
Read/Write
Initial Value
ADTS3
1
1
1
1
For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock
source.
ADC Auto Trigger Source Selection for amplified conversions
ADTS2
1
1
1
1
ADC7
7
R
R
0
0
-
ADC6
R
R
6
0
0
-
ADTS1
0
0
1
1
ADC5
R
R
5
0
0
-
0
1
0
1
ADC4
ADTS0
R
R
4
0
0
-
ADC3
3
R
R
0
0
-
Description
Reserved
Reserved
Reserved
Reserved
ADC2
R
R
2
0
0
-
ADC9
ADC1
R
R
1
0
0
ADC8
ADC0
R
R
0
0
0
4378C–AVR–09/08
ADCH
ADCL