TINY88-15MZ Atmel, TINY88-15MZ Datasheet - Page 18
TINY88-15MZ
Manufacturer Part Number
TINY88-15MZ
Description
MCU AVR 8KB FLASH 12MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.TINY88-15MZ.pdf
(246 pages)
Specifications of TINY88-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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5.3
5.3.1
18
EEPROM Data Memory
ATtiny88 Automotive
EEPROM Read/Write Access
Figure 5-3.
ATtiny88 devices contain 64 bytes of data EEPROM memory, organized as a separate data
space in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the
following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
“Memory Programming” on page 191
in SPI or Parallel Programming mode.
The EEPROM Access Registers are located in I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
“Preventing EEPROM Corruption” on page 21
“Atomic Byte Programming” on page 19
CC
Address
clk
is likely to rise or fall slowly on power-up/down. This causes the device for some
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
Compute Address
T1
Memory Access Instruction
contains a detailed description on EEPROM Programming
Address valid
and
for details on how to avoid problems in these
T2
Table
“Split Byte Programming” on page 19
5-2. A self-timing function, however,
Next Instruction
T3
9157B–AVR–01/10
for
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