TINY88-15MZ Atmel, TINY88-15MZ Datasheet - Page 31
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
TINY88-15MZ
Manufacturer Part Number
TINY88-15MZ
Description
MCU AVR 8KB FLASH 12MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.TINY88-15MZ.pdf
(246 pages)
Specifications of TINY88-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.6
6.7
9157B–AVR–01/10
Clock Output Buffer
System Clock Prescaler
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal
oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
The ATtiny88 has a system clock prescaler, and the system clock can be divided by setting the
“CLKPR – Clock Prescale Register” on page
tem clock frequency and the power consumption when the requirement for processing power is
low. This can be used with all clock source options, and it will affect the clock frequency of the
CPU and all synchronous peripherals. clk
as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler – even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must befollowed to
change the CLKPS bits:
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
CLKPR to zero.
Table 6-9 on page
33.
I/O
, clk
32. This feature can be used to decrease the sys-
ADC
, clk
ATtiny88 Automotive
CPU
, and clk
FLASH
are divided by a factor
31
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