PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 108

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
FIGURE 10-12:
TABLE 10-8:
DS41203E-page 106
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
Name
TX/CK pin
TX/CK pin
SREN bit
CREN bit
bit SREN
RCIF bit
RXREG
RX/DT
Write to
Read
pin
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
EUSART Receive Data Register
EUSART Transmit Data Register
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
BRG15
SPEN
BRG7
CSRC
Bit 7
EEIE
EEIF
GIE
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
BRG14
RCIDL
BRG6
Bit 6
PEIE
ADIE
ADIF
RX9
TX9
—
bit 0
BRG13
TRISC5
SREN
BRG5
TXEN
Bit 5
RCIE
RCIF
T0IE
—
bit 1
BRG12
TRISC4
CREN
BRG4
SYNC
SCKP
Bit 4
INTE
C2IE
C2IF
bit 2
ADDEN
SENDB
BRG16
BRG11
TRISC3
BRG3
Bit 3
RAIE
C1IE
C1IF
bit 3
BRG10
TRISC2
FERR
BRG2
BRGH
OSFIE
OSFIF
Bit 2
T0IF
—
bit 4
TRISC1
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
TXIE
TXIF
bit 5
ABDEN
TMR1IE
TMR1IF
TRISC0
RX9D
BRG0
BRG8
TX9D
Bit 0
RAIF
© 2009 Microchip Technology Inc.
bit 6
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
0000 0000
0000 0010
POR, BOR
--11 1111
Value on
bit 7
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
0000 0000
0000 0010
--11 1111
Value on
all other
Resets
‘0’