ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 46

• Manufacturer Part Number: ATMEGA88-20MUR
• Description: MCU AVR 8K FLASH 20MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88-20MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: MLF EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3
2545T–AVR–05/11
Power-on reset
Figure 11-1. Reset logic.
A power-on reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in
V
well as to detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the
power-on reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
Figure 11-2. MCU start-up, RESET tied to V
CC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
INTERNAL
TIME-OUT
BODLEVEL [2..0]
RSTDISBL
CC
RESET
RESET
V
decreases below the detection level.
CC
“System and reset characteristics” on page
Pull-up resistor
FILTER
SPIKE
V
V
POT
RST
CC
t
TOUT
CKSEL[3:0]
rise. The RESET signal is activated again, without any delay,
Power-on reset
Reset circuit
SUT[1:0]
reset circuit
Brown-out
Watchdog
Watchdog
oscillator
generator
circuit
timer
Clock
CC.
CK
register (MCUSR)
MCU status
DATA BUS
Delay counters
307. The POR is activated whenever
ATmega48/88/168
TIMEOUT
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