ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 68
ATMEGA88-20MUR
Manufacturer Part Number
ATMEGA88-20MUR
Description
MCU AVR 8K FLASH 20MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88-20MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
MLF EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.2.2
13.2.3
2545T–AVR–05/11
EIMSK – External interrupt mask register
EIFR – External interrupt flag register
• Bit 7..2 – Res: Reserved bits
These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero.
• Bit 1 – INT1: External interrupt request 1 enable
When the INT1 bit is set (one) and the I-bit in the status register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The interrupt sense control1 bits 1/0 (ISC11 and ISC10) in the
external interrupt control register A (EICRA) define whether the external interrupt is activated on
rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an inter-
rupt request even if INT1 is configured as an output. The corresponding interrupt of external
interrupt request 1 is executed from the INT1 interrupt vector.
• Bit 0 – INT0: External interrupt request 0 enable
When the INT0 bit is set (one) and the I-bit in the status register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The interrupt sense Control0 bits 1/0 (ISC01 and ISC00) in the
external interrupt control register A (EICRA) define whether the external interrupt is activated on
rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an inter-
rupt request even if INT0 is configured as an output. The corresponding interrupt of external
interrupt request 0 is executed from the INT0 interrupt vector.
• Bit 7..2 – Res: Reserved bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 1 – INTF1: External interrupt flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-
responding interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External interrupt flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
Bit
0x1D (0x3D)
Read/write
Initial value
Bit
0x1C (0x3C)
Read/write
Initial value
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
ATmega48/88/168
R
R
2
–
0
2
–
0
INTF1
INT1
R/W
R/W
1
0
1
0
INTF0
INT0
R/W
R/W
0
0
0
0
EIMSK
EIFR
68
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