ATA6617-P3PW Atmel, ATA6617-P3PW Datasheet - Page 298
ATA6617-P3PW
Manufacturer Part Number
ATA6617-P3PW
Description
MCU W/LIN TX/5V REG/WTCDG 38VQFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6617-EK.pdf
(308 pages)
Specifications of ATA6617-P3PW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DATA TRANSFER INSTRUCTIONS
MCU CONTROL INSTRUCTIONS
Mnemonics
BREAK
SLEEP
MOVW
PUSH
WDR
MOV
SPM
NOP
LPM
LPM
LPM
OUT
POP
LDD
LDD
LDS
STD
STD
STS
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Instruction Set Summary (Continued)
Atmel ATA6616/ATA6617
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Z+
Rd, Rr
Rd, Rr
Rd, -Z
X+, Rr
- X, Rr
Y+, Rr
Z+, Rr
- Y, Rr
Rd, K
Rd, X
Rd, Y
-Z, Rr
Rd, P
Rd, Z
Rd, k
Rd, Z
X, Rr
Z, Rr
Y, Rr
k, Rr
P, Rr
Rd
Rr
Load Program Memory and Post-Inc
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Move Between Registers
Pop Register from Stack
Load Direct from SRAM
Store Program Memory
Push Register on Stack
Load Program Memory
Load Program Memory
Store Direct to SRAM
Copy Register Word
Watchdog Reset
Load Immediate
Store Indirect
Store Indirect
Store Indirect
No Operation
Load Indirect
Load Indirect
Load Indirect
Description
Out Port
In Port
Sleep
Break
(see specific descr. for WDR/timer)
(see specific descr. for Sleep
For On-chip Debug Only
Rd+1:Rd
Rd
Rd
X
Y
(X)
(Y)
Z
X
Y
(Z)
Z
Rd
Rd
Rd
Rd
Rd
STACK
(Y + q)
(Z)
(Z + q)
Operation
X - 1, Rd
Y - 1, Rd
Z - 1, Rd
X - 1, (X)
Y - 1, (Y)
Z - 1, (Z)
Rd
Rd
Rd
function)
(X), X
(Y), Y
Rd
R0
Rd
Rd
(X)
(Y)
(Z)
Rd
(k)
Rr, X
Rr, Y
Rr, Z
Rd
(Z), Z
(Z), Z
P
STACK
(Y + q)
(Z + q)
R1:R0
Rr
(X)
(Y)
(Z)
(Z)
(Z)
Rr
Rr
Rr
(k)
Rr
Rr
Rr+1:Rr
P
K
Rr
Rr
Rr
Z + 1
X + 1
Y + 1
X + 1
Y + 1
Z+1
Z+1
(X)
(Y)
(Z)
Rr
Rr
Rr
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
9132D–AUTO–12/10
#Clocks
N/A
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
1
1
1
-
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