DSPIC33FJ12GP202-I/SS Microchip Technology, DSPIC33FJ12GP202-I/SS Datasheet - Page 104
DSPIC33FJ12GP202-I/SS
Manufacturer Part Number
DSPIC33FJ12GP202-I/SS
Description
IC DSPIC MCU/DSP 12K 28SSOP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ12GP201-ISO.pdf
(249 pages)
3.DSPIC33FJ12GP201-ISO.pdf
(12 pages)
4.DSPIC33FJ12GP202-IML.pdf
(242 pages)
Specifications of DSPIC33FJ12GP202-I/SS
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Package
28SSOP
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- DSPIC33FJ12GP201-ISO PDF datasheet
- DSPIC33FJ12GP201-ISO PDF datasheet #2
- DSPIC33FJ12GP201-ISO PDF datasheet #3
- DSPIC33FJ12GP202-IML PDF datasheet #4
- Current page: 104 of 249
- Download datasheet (4Mb)
dsPIC33FJ12GP201/202
8.3
Fail-Safe Clock Monitor (FSCM)
The FSCM allows the device to continue to operate
even in the event of an oscillator failure. The FSCM
function is enabled by programming. If the FSCM
function is enabled, the LPRC internal oscillator runs at
all times (except during Sleep mode) and is not subject
to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Preliminary
© 2009 Microchip Technology Inc.
DS70264D-page 102
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