DSPIC33FJ12GP202-I/SS Microchip Technology, DSPIC33FJ12GP202-I/SS Datasheet - Page 63

• Manufacturer Part Number: DSPIC33FJ12GP202-I/SS
• Description: IC DSPIC MCU/DSP 12K 28SSOP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12GP202-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SSOP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 6-2:
TABLE 6-2:
© 2009 Microchip Technology Inc.
V
T
V
T
T
T
Symbol
POR
BOR
PWRT
FSCM
POR
BOR
Oscillator Clock
Device Status
1.
2.
3.
4.
5.
6.
POR Reset
BOR Reset
SYSRST
POR threshold
POR extension
time
BOR threshold
BOR extension
time
Programmable
power-up time
delay
Fail-safe Clock
Monitor Delay
FSCM
POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V
the V
BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
and the delay T
PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (T
after a BOR. The delay T
operation. After the delay T
generating clock cycles.
Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table 6-1. Refer to
Section 8.0 “Oscillator Configuration” for more information.
When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO
instruction at the Reset address, which redirects program execution to the appropriate start-up routine.
The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay
T
FSCM
V
DD
POR
Parameter
elapsed.
OSCILLATOR DELAY
threshold and the delay T
1
SYSTEM RESET TIMING
BOR
has elapsed. The delay T
2
PWRT
T
PWRT
1.8V nominal
30 μs maximum
2.5V nominal
100 μs maximum
0-128 ms nominal
900 μs maximum
V
POR
POR
ensures that the system power supplies have stabilized at the appropriate level for full-speed
has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start
POR
Value
has elapsed.
BOR
Preliminary
Vbor
ensures the voltage regulator output becomes stable.
V
BOR
dsPIC33FJ12GP201/202
T
PWRT
T
3
BOR
Reset
Time
Note:
T
OSCD
When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all
specification.
T
OST
4
operating
DD
T
crosses the V
LOCK
parameters
DS70264D-page 61
5
BOR
6
Run
DD
threshold
T
crosses
FSCM
PWRT
within
)