PIC16F883-I/ML Microchip Technology, PIC16F883-I/ML Datasheet - Page 159
![IC PIC MCU FLASH 4KX14 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F883-I/ML
Manufacturer Part Number
PIC16F883-I/ML
Description
IC PIC MCU FLASH 4KX14 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.MCP1631RD-MCC2.pdf
(328 pages)
3.PIC16F882-ISS.pdf
(16 pages)
4.PIC16F882-ISS.pdf
(36 pages)
Specifications of PIC16F883-I/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
MSSP, EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164120-3
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28QFN EP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP1631RD-MCC2 - REFERENCE DESIGN MCP1631HVXLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F883-I/ML
Manufacturer:
MICROCHIP
Quantity:
1 200
- PIC16F616T-ISL PDF datasheet
- MCP1631RD-MCC2 PDF datasheet #2
- PIC16F882-ISS PDF datasheet #3
- PIC16F882-ISS PDF datasheet #4
- Current page: 159 of 328
- Download datasheet (6Mb)
12.1.2.4
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
12.1.2.5
The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
12.1.2.6
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
© 2009 Microchip Technology Inc.
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
Receive Framing Error
Receive Overrun Error
Receiving 9-bit Characters
PIC16F882/883/884/886/887
12.1.2.7
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
Address Detection
DS41291F-page 157
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