PIC12C671-10/SM Microchip Technology, PIC12C671-10/SM Datasheet - Page 308
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PIC12C671-10/SM
Manufacturer Part Number
PIC12C671-10/SM
Description
IC MCU OTP 1KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C671-10/SM
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
PIC12C671-10/SMR
PIC12C671-10/SMR
PIC12C671-10/SMR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12C671-10/SM
Manufacturer:
Microchip Technology
Quantity:
135
- Current page: 308 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.9
17.4.9.1
DS31017A-page 17-32
I
WCOL Status Flag
2
C Master Mode Start Condition Timing
To initiate a START condition the user sets the start condition enable bit, SEN (SSPCON2<0>).
If the SDA and SCL pins are sampled high, the baud rate generator is re-loaded with the contents
of SSPADD<6:0>, and starts its count. If SCL and SDA are both sampled high when the baud
rate generator times out (T
low while SCL is high is the START condition, and causes the S bit (SSPSTAT<3>) to be set. Fol-
lowing this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes
its count. When the baud rate generator times out (T
automatically cleared by hardware, the baud rate generator is suspended leaving the SDA line
held low, and the START condition is complete.
If the user writes the SSPBUF when an START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write doesn’t occur).
Figure 17-20: First Start Bit Timing
Note:
Note:
Write to SEN bit occurs here.
If at the beginning of START condition the SDA and SCL pins are already sampled
low, or if during the START condition the SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag,BCLIF, is
set, the START condition is aborted, and the I
Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2
is disabled until the START condition is complete.
SDA
SCL
BRG
Preliminary
), the SDA pin is driven low. The action of the SDA being driven
SDA = 1,
SCL = 1
T
BRG
Set S bit (SSPSTAT<3>)
S
T
BRG
At completion of start bit,
Hardware clears SEN bit
BRG
and sets SSPIF bit
2
) the SEN bit (SSPCON2<0>) will be
C module is reset into its IDLE state.
T
Write to SSPBUF occurs here
BRG
1st Bit
1997 Microchip Technology Inc.
T
BRG
2nd Bit
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