PIC16LF627A-I/ML Microchip Technology, PIC16LF627A-I/ML Datasheet - Page 104
![IC MCU FLASH 1KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF627A-I/ML
Manufacturer Part Number
PIC16LF627A-I/ML
Description
IC MCU FLASH 1KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF627A-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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PIC16F627A/628A/648A
14.4.5
On power-up, the time out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
OST is activated. The total time out will vary based on
oscillator configuration and PWRTE bit Status. For
example, in RC mode with PWRTE bit set (PWRT
disabled), there will be no time out at all. Figure 14-8,
Figure 14-11 and Figure 14-12 depict time out
sequences.
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 14-11). This is useful for testing purposes
or to synchronize more than one PIC16F627A/628A/
648A device operating in parallel.
Table 14-6 shows the Reset conditions for some
special registers, while Table 14-7 shows the Reset
conditions for all the registers.
TABLE 14-3:
TABLE 14-4:
DS40044G-page 104
Legend:
Oscillator Configuration
POR
0
0
0
1
1
1
1
1
XT, HS, LP
INTOSC
RC, EC
TIME OUT SEQUENCE
u = unchanged, x = unknown
BOR
X
X
X
0
1
1
1
1
TIME OUT IN VARIOUS SITUATIONS
STATUS/PCON BITS AND THEIR SIGNIFICANCE
TO
1
0
X
X
0
0
u
1
PWRTE = 0
1024•T
72 ms +
72 ms
72 ms
PD
1
X
0
X
u
0
u
0
Power-up Timer
OSC
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
PWRTE = 1
1024•T
—
—
OSC
14.4.6
The PCON/Status register, PCON (address 8Eh), has
two bits.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0
indicating that a brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BOREN bit = 0 in the Configuration Word).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (V
gone too low).
PWRTE = 0
1024•T
72 ms +
72 ms
72 ms
Brown-out Reset
POWER CONTROL (PCON) STATUS
REGISTER
Condition
OSC
PWRTE = 1
1024•T
© 2009 Microchip Technology Inc.
—
—
OSC
Wake-up from
1024•T
DD
Sleep
6 μs
may have
—
OSC
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