PIC16LF627A-I/ML Microchip Technology, PIC16LF627A-I/ML Datasheet - Page 73
![IC MCU FLASH 1KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF627A-I/ML
Manufacturer Part Number
PIC16LF627A-I/ML
Description
IC MCU FLASH 1KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF627A-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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12.0
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) is also known as a Serial
Communications Interface (SCI). The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices such as A/D
or D/A integrated circuits, Serial EEPROMs, etc.
REGISTER 12-1:
© 2009 Microchip Technology Inc.
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Synchronous mode
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode
Synchronous mode
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
Legend:
R = Readable bit
-n = Value at POR
R/W-0
CSRC
Note 1: SREN/CREN overrides TXEN in SYNC mode.
1 = High speed
0 = Low speed
Unused in this mode
Don’t care
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
R/W-0
TX9
R/W-0
TXEN
(1)
W = Writable bit
‘1’ = Bit is set
PIC16F627A/628A/648A
R/W-0
SYNC
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous
• Synchronous
Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be
set in order to configure pins RB2/TX/CK and RB1/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
Register 12-1 shows the Transmit Status and Control
Register (TXSTA) and Register 12-2 shows the
Receive Status and Control Register (RCSTA).
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
–
–
Master (half-duplex)
Slave (half-duplex)
R/W-0
BRGH
x = Bit is unknown
TRMT
R-1
DS40044G-page 73
R/W-0
TX9D
bit 0
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