ATTINY44-15SSZ Atmel, ATTINY44-15SSZ Datasheet - Page 45

• Manufacturer Part Number: ATTINY44-15SSZ
• Description: IC MCU AVR 4K FLASH 15MHZ 14SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15SSZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / Rohs Status: Details
• Other names: Q3447517

9.9
9.9.1
9.9.2
7701E–AVR–02/11
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
Safety Level 2
To prevent unintentional disabling of the watchdog or unintentional change of time-out period,
two different safety levels are selected by the WDTON fuse, as shown in Table 9-2. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45
details.
Table 9-2.
Figure 9-7.
The sequence for changing configuration differs slightly between the two safety levels. Sepa-
rate procedures are described for each level.
In this mode, the watchdog timer is initially disabled, but can be enabled by writing the WDE
bit to logical one without any restriction. A timed sequence is needed when disabling an
enabled watchdog timer. To disable an enabled watchdog timer, the following procedure must
be followed:
1. In the same operation, write a logical one to WDCE and WDE. A logical one must be
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits
In this mode, the watchdog timer is always enabled, and the WDE bit will always read as logi-
cal one. A timed sequence is needed when changing the watchdog time-out period. To
change the watchdog time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
WDTON
Unprogrammed
Programmed
written to WDE regardless of the previous value of the WDE bit.
as desired, but with the WDCE bit cleared.
always is set, the WDE must be written to one to start the timed sequence.
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
WDT Configuration as a Function of the Fuse Settings of WDTON
Watchdog Timer
Safety
Level
1
2
WATCHDOG
OSCILLATOR
Atmel ATtiny24/44/84 [Preliminary]
RESET
128 kHz
WDP0
WDP1
WDP2
WDP3
WDE
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
MCU RESET
PRESCALER
WATCHDOG
How to Change
Time-out
No limitations
Timed sequence
for
45