PIC18F45K20-I/P Microchip Technology, PIC18F45K20-I/P Datasheet - Page 8

• Manufacturer Part Number: PIC18F45K20-I/P
• Description: IC PIC MCU FLASH 16KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F24K20/25K20/44K20/45K20
25. Module: Configuration Bits
26. Module: EUSART
27. Module: PORTB
DS80425G-page 8
Bit 3 of CONFIG3H defaults to ‘0’ after a Bulk
Erase instead of ‘1’ as specified in the data sheet.
Work around
Program the HFOFST bit to the desired state after
a Bulk Erase. All MPLAB
currently perform this way.
Affected Silicon Revisions
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
an invalid Start bit less than 1/8th of a bit time is
received. The RCIDL bit will then stay low improp-
erly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
Setting a PORTB interrupt-on-change enable bit of
the IOCB register while the corresponding PORTB
input is high will cause an RBIF interrupt.
Work around
Set the IOCB bits to the desired configuration, then
read PORTB to clear the mismatch latches.
Finally, clear the RBIF bit before setting the RBIE
bit.
Affected Silicon Revisions
X
X
X
X
X
X
X
X
X
X
X
X
®
IDE programming tools
X
X
X
X
28. Module: ADC
29. Module: ECCP
30. Module: ECCP
• The potential for failures increases over the life
• The potential for failures is highest at low V
1. Restrict the input voltage to less than 1/2 of the
2. Use manual acquisition time (ACQT<2:0> =
After extended stress, the Most Significant bit
(MSb) of the ADC conversion result can become
stuck at ‘0’. Conversions resulting in code 511 or
less are still accurate, but conversions that should
result in codes greater than 511 are, instead,
pinned at 511.
The potential for failures is a function of several
factors:
Work around
ADC voltage reference so that the expected
result is always a code less than or equal to 511.
000) and put the part to Sleep after each
conversion.
Affected Silicon Revisions
Changing direction in Full-Bridge mode inserts a
dead-band time of 4/F
instead of 1/F
the data sheet.
Work around
None.
Affected Silicon Revisions
ECCP – In Full-Bridge mode when PR2 =
CCPR1L and DC1B[1:0] <>‘00’ and the direction
is changed, then the dead time before the modu-
lated output starts is compromised. The modulated
of the part. No failures have ever been seen for
accelerated stress estimated to be equivalent
to 34 years at room temperature. The failure
rate after accelerated stress estimated to be
equivalent to 146 years at room temperature
can be as high as 10% for V
to failure will decrease as the operating
temperature increases.
and decreases as V
X
X
OSC
X
* TMR2 Prescale as specified in
 2010 Microchip Technology Inc.
DD
X
increases.
OSC
X
X
DD
= 1.8V. The time
* TMR2 Prescale
X
X
X
X
DD
X