PIC16LF872T-I/SS Microchip Technology, PIC16LF872T-I/SS Datasheet - Page 16
![IC MCU FLASH 2KX14 EE A/D 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16LF872T-I/SS
Manufacturer Part Number
PIC16LF872T-I/SS
Description
IC MCU FLASH 2KX14 EE A/D 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16C770-ISO.pdf
(8 pages)
2.PIC16F872-ISO.pdf
(168 pages)
3.PIC16F872-ISO.pdf
(5 pages)
4.PIC16F872-ISO.pdf
(6 pages)
Specifications of PIC16LF872T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16C770-ISO PDF datasheet
- PIC16F872-ISO PDF datasheet #2
- PIC16F872-ISO PDF datasheet #3
- PIC16F872-ISO PDF datasheet #4
- Current page: 16 of 168
- Download datasheet (3Mb)
PIC16F872
2.2.2.3
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3:
DS30221C-page 14
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON Register
INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
- n = Value at POR
R/W-0
GIE
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
R/W-0
PEIE
TMR0IE
R/W-0
W = Writable bit
’1’ = Bit is set
R/W-0
INTE
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
RBIE
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
TMR0IF
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/W-0
INTF
R/W-x
RBIF
bit 0
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