PIC16LF872T-I/SS Microchip Technology, PIC16LF872T-I/SS Datasheet - Page 18
![IC MCU FLASH 2KX14 EE A/D 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16LF872T-I/SS
Manufacturer Part Number
PIC16LF872T-I/SS
Description
IC MCU FLASH 2KX14 EE A/D 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16C770-ISO.pdf
(8 pages)
2.PIC16F872-ISO.pdf
(168 pages)
3.PIC16F872-ISO.pdf
(5 pages)
4.PIC16F872-ISO.pdf
(6 pages)
Specifications of PIC16LF872T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16C770-ISO PDF datasheet
- PIC16F872-ISO PDF datasheet #2
- PIC16F872-ISO PDF datasheet #3
- PIC16F872-ISO PDF datasheet #4
- Current page: 18 of 168
- Download datasheet (3Mb)
PIC16F872
2.2.2.5
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
DS30221C-page 16
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
PIR1 Register
PIR1 REGISTER (ADDRESS: 0Ch)
bit 7
Reserved: Always maintain these bits clear
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
Reserved: Always maintain these bits clear
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning
0 = No SSP interrupt condition has occurred
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode: Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
- n = Value at POR
reserved
R/W-0
• SPI
• I
• I
from the Interrupt Service Routine. The conditions that will set this bit are:
2
2
C Master
- A transmission/reception has taken place
C Slave
- A transmission/reception has taken place
- A transmission/reception has taken place
- The initiated START condition was completed by the SSP module
- The initiated STOP condition was completed by the SSP module
- The initiated Restart condition was completed by the SSP module
- The initiated Acknowledge condition was completed by the SSP module
- A START condition occurred while the SSP module was idle (multi-master system)
- A STOP condition occurred while the SSP module was idle (multi-master system)
R/W-0
ADIF
W = Writable bit
’1’ = Bit is set
reserved
R/W-0
reserved
R/W-0
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPIF
R/W-0
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
CCP1IF
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
TMR1IF
R/W-0
bit 0
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