DSPIC30F2010-20E/SP Microchip Technology, DSPIC30F2010-20E/SP Datasheet - Page 196

• Manufacturer Part Number: DSPIC30F2010-20E/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F2010
PWM
PWM Duty Cycle Comparison Units ................................... 85
PWM FLTA Pins.................................................................. 88
PWM Operation During CPU Idle Mode.............................. 89
PWM Operation During CPU Sleep Mode .......................... 89
PWM Output and Polarity Control ....................................... 88
PWM Output Override......................................................... 87
PWM Period ........................................................................ 84
PWM Special Event Trigger ................................................ 89
PWM Time Base ................................................................. 83
PWM Update Lockout ......................................................... 88
Q
QEA/QEB Input Characteristics ........................................ 171
QEI Module
Quadrature Decoder Timing Requirements ...................... 171
Quadrature Encoder Interface (QEI) Module ...................... 75
Quadrature Encoder Interface Interrupts ............................ 78
Quadrature Encoder Interface Logic ................................... 76
R
Reader Response ............................................................. 200
Reset......................................................................... 123, 129
Reset Sequence.................................................................. 39
Reset Timing Characteristics ............................................ 162
Reset Timing Requirements.............................................. 163
Resets
RTSP Operation.................................................................. 44
DS70118G-page 194
Register Map............................................................... 90
Duty Cycle Register Buffers ........................................ 86
Enable Bits .................................................................. 88
Fault States ................................................................. 88
Modes ......................................................................... 88
Output Pin Control ...................................................... 88
Complementary Output Mode ..................................... 87
Synchronization .......................................................... 87
Postscaler ................................................................... 89
Continuous Up/Down Counting Modes ....................... 83
Double Update Mode .................................................. 84
Free Running Mode .................................................... 83
Postscaler ................................................................... 84
Prescaler ..................................................................... 84
Single-Shot Mode ....................................................... 83
External Clock Timing Requirements........................ 167
Index Pulse Timing Characteristics........................... 172
Index Pulse Timing Requirements ............................ 172
Operation During CPU Idle Mode ............................... 78
Operation During CPU Sleep Mode ............................ 77
Register Map............................................................... 79
Timer Operation During CPU Idle Mode ..................... 78
Timer Operation During CPU Sleep Mode.................. 77
Reset Sources ............................................................ 39
BOR, Programmable................................................. 131
POR .......................................................................... 129
POR with Long Crystal Start-up Time ....................... 131
Cycle-by-Cycle.................................................... 88
Latched ............................................................... 88
Operating without FSCM and PWRT ................ 131
S
Sales and Support ............................................................ 201
Serial Peripheral Interface. See SPI
Simple Capture Event Mode
Simple OC/PWM Mode Timing Requirements ................. 169
Simple Output Compare Match Mode ................................ 72
Simple PWM Mode ............................................................. 72
Single Pulse PWM Operation ............................................. 87
Software Simulator (MPLAB SIM) .................................... 146
Software Stack Pointer, Frame Pointer .............................. 10
SPI ...................................................................................... 91
SPI Mode
SPI Module ......................................................................... 91
SPI Operation During CPU Idle Mode ................................ 93
SPI Operation During CPU Sleep Mode............................. 93
STATUS Register ............................................................... 10
Subtracter ........................................................................... 15
Symbols used in Opcode Descriptions ............................. 138
System Integration............................................................ 123
T
Temperature and Voltage Specifications
Timer1 Module.................................................................... 57
Capture Buffer Operation............................................ 68
Capture Prescaler....................................................... 68
Hall Sensor Mode ....................................................... 68
Input Capture in CPU Idle Mode................................. 69
Timer2 and Timer3 Selection Mode............................ 68
Input Pin Fault Protection ........................................... 72
Period ......................................................................... 73
CALL Stack Frame ..................................................... 27
Slave Select Synchronization ..................................... 93
SPI1 Register Map...................................................... 94
Framed SPI Support ................................................... 91
Operating Function Description .................................. 91
SDOx Disable ............................................................. 91
Timing Characteristics
Timing Requirements
Word and Byte Communication .................................. 91
Data Space Write Saturation ...................................... 17
Overflow and Saturation ............................................. 15
Round Logic ............................................................... 16
Write Back .................................................................. 16
Overview................................................................... 123
Register Map ............................................................ 135
AC............................................................................. 157
DC ............................................................................ 149
16-bit Asynchronous Counter Mode ........................... 57
16-bit Synchronous Counter Mode ............................. 57
16-bit Timer Mode....................................................... 57
Gate Operation ........................................................... 58
Interrupt ...................................................................... 59
Operation During Sleep Mode .................................... 58
Prescaler .................................................................... 58
Real-Time Clock ......................................................... 59
Register Map .............................................................. 60
Master Mode (CKE = 0).................................... 173
Master Mode (CKE = 1).................................... 174
Slave Mode (CKE = 1).............................. 175, 176
Master Mode (CKE = 0).................................... 173
Master Mode (CKE = 1).................................... 174
Slave Mode (CKE = 0)...................................... 175
Slave Mode (CKE = 1)...................................... 177
RTC Interrupts .................................................... 59
RTC Oscillator Operation ................................... 59
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