PIC18F87J11T-I/PT Microchip Technology, PIC18F87J11T-I/PT Datasheet
PIC18F87J11T-I/PT
Specifications of PIC18F87J11T-I/PT
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PIC18F87J11T-I/PT Summary of contents
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... PGD Legend Input Output Power Note 1: All power supply and ground pins must be connected, including analog supplies (AV ( © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX 2.0 PROGRAMMING OVERVIEW OF THE PIC18F6XJXX/8XJXX The PIC18F6XJXX/8XJXX devices are programmed using In-Circuit Serial Programming™ (ICSP™). This programming PIC18F6XJXX/8XJXX devices in all package types ...
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... RF6 12 RF5 13 RF4 14 RF3 15 RF2 DS39644E-page 2 • PIC18F65J15 • PIC18F64J11 • PIC18F65J11 • PIC18F63J90 • PIC18F65J10 • PIC18F63J11 • PIC18F64J90 PIC18F6XJXX RB0 47 RB1 46 RB2 45 RB3 44 RB4 43 RB5 RB6/KBI2/PGC OSC2 40 39 OSC1 RB7/KBI3/PGD 37 RC5 36 RC4 35 RC3 34 RC2 33 © 2006 Microchip Technology Inc. ...
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... RG3 8 MCLR 9 RG4 DDCORE CAP 12 RF7 13 RF6 14 RF5 15 RF4 16 RF3 17 RF2 18 RH7 19 RH6 © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX • PIC18F85J15 • PIC18F84J11 • PIC18F85J11 • PIC18F83J90 • PIC18F85J10 • PIC18F83J11 • PIC18F84J90 PIC18F8XJXX RJ2 60 RJ3 59 RB0 58 RB1 57 RB2 56 55 RB3 ...
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... Note 1: These are typical operating voltages. Refer to Section 6.0 “AC/DC Characteristics and Timing Requirements for Program/Verify Test Mode”. CONNECTIONS FOR THE ON-CHIP REGULATOR ): DD (1) 3.3V PIC18F6XJXX/8XJXX V DD ENVREG V /V DDCORE CAP (1) 3.3V PIC18F6XJXX/8XJXX V DD ENVREG V /V DDCORE CAP V SS © 2006 Microchip Technology Inc. ...
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... Device ID bits. These bits may be used by the program- mer to identify what device type is being programmed and are described in Section 5.1 “Device ID Word”. These Device ID bits read out normally, even after code protection. © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX TABLE 2-2: PROGRAM MEMORY SIZES FOR PIC18F6XJXX/8XJXX ...
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... Configuration Configuration Space Space Configuration Configuration Configuration Words Words Configuration Configuration Configuration Space Space Device IDs Device IDs Device IDs (1) 000000h 007FFFh 00BFFFh 00FFFFh 017FFFh 01FFFFh 1FFFFFh 200000h Space 2FFFFFh 300000h Words (2) 300007h Space 3FFFFEh 3FFFFFh © 2006 Microchip Technology Inc. ...
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... Memory spaces are read-only (Device IDs) or cannot be directly programmed by ICSP™ (Configuration Words). Note 1: Sizes of memory areas are not to scale. Sizes of accessible memory areas are enhanced to show detail. 2: Configuration Words at 300006h and 300007h are not implemented on PIC18FXXJ11/XXJ90 devices. © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX Code Memory Code Memory Flash Conf. Words Flash Conf ...
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... PGC and PGD before removing Program/Verify Entry Code = 4D434850h ... b31 b30 b29 b28 b27 b3 P2B P2A , There is no minimum time requirement . After V is removed, an interval must P20 P12 © 2006 Microchip Technology Inc. ...
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... Command © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX Throughout this specification, commands and data are presented as illustrated in Table 2-4. The 4-bit command is shown Most Significant bit (MSb) first. The command operand, or “Data Payload”, is shown <MSB><LSB>. Figure 2-9 demonstrates how to serially present a 20-bit command/operand to the device ...
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... NOP 00 00 Hold PGD low until erase 00 00 completes. BULK ERASE FLOW Start Write 0101h to 3C0005h Write 8080h to 3C0004h to Erase Entire Device Delay P11 + P10 Time Done P10 P11 Erase Time 16-Bit Data Payload © 2006 Microchip Technology Inc. ...
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... To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented each iteration of the loop. © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX The programming duration is externally timed and is controlled by PGC. After a Start Programming command is issued (4-bit command, ‘1111’), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9 ...
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... Bytes Written? Yes Start Write Sequence and Hold PGC High Until Done and Wait P9 Hold PGC Low for Time P10 All No Locations Done? Yes Done P5A 4-Bit Command PGD = Input P10 Programming Time 16-Bit Data Payload © 2006 Microchip Technology Inc. ...
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... To continue modifying data, repeat Step 5, where the Address Pointer is incremented by the appropriate number of bytes at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the program memory. Step 7: Disable writes. 0000 94 A6 © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX 3.2.2 CONFIGURATION WORD PROGRAMMING ...
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... Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output P5A MSb Fetch Next 4-Bit Command PGD = Input © 2006 Microchip Technology Inc. ...
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... Yes All No Code Memory Verified? Yes Done © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX 4.3 Blank Check The term “Blank Check” means to verify that the device has no programmed memory cells. All memories must be verified: code memory and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. A “ ...
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... XXXFEh 300006h XXXFFh 300007h Default/ Bit 1 Bit 0 Unprogrammed Value — WDTEN 111- ---1 — — ---- 01-- FOSC1 FOSC0 11-- -111 WDTPS1 WDTPS0 ---- 1111 — — 1111 1--- (3, 5) ECCPMX CCP2MX ---- --11 REV1 REV0 See Table 5-4 DEV4 DEV3 See Table 5-4 © 2006 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F6XJXX/8XJXX Description purpose I/O pins Debug (Legacy mode) of FOSC1:FOSC0; INTRC selected when OSCCON<1:0> OSCCON<1:0> OSC2 DS39644E-page 17 ...
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... ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (all devices) DS39644E-page 18 Description 000000h ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 or with RB3 in Extended Microcontroller mode (80-pin devices only) © 2006 Microchip Technology Inc. ...
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... PIC18F85J10 PIC18F85J11 PIC18F85J15 PIC18F85J90 PIC18F86J10 PIC18F86J15 PIC18F87J10 Legend: The ‘x’s in DEVID1 are reserved for the device revision code. © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX FIGURE 5-1: READ DEVICE ID WORD FLOW Start Set TBLPTR = 3FFFFE Read Low Byte with Post-Increment Read High Byte ...
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... ENVREG pin if the on-chip voltage DD should always be within ±0. Units Conditions V (Note 1) V Normal programming (Note 2) μ meet AC specifications μF Required for controller core operation when voltage regulator is enabled and V , respectively. SS © 2006 Microchip Technology Inc. ...
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... PGD to Second MCLR ↑ Note 1: V must be supplied to the V DDCORE Section 2.1.1 “On-Chip Voltage Regulator” for more information must also be supplied to the AV DD regulator is used. AV and AV DD © 2006 Microchip Technology Inc. PIC18F6XJXX/8XJXX Min Max — 1.0 100 — 40 — 40 — 15 — ...
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... PIC18F6XJXX/8XJXX NOTES: DS39644E-page 22 © 2006 Microchip Technology Inc. ...
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... PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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